On a multiple chip seal, the nominal aggregate size of each succeeding course should be __________.

On a multiple chip seal, the nominal aggregate size of each succeeding course should be __________.

• A. Same as previous
• B. Double the size of the previous course
• C. Half the size of the previous course
• D. Quarter the size of the previous course

Answer: (C)

In a multiple chip seal application, the nominal aggregate size of each succeeding course being half the size of the previous course is a well-established practice aimed at achieving a proper interlock and effective compaction. Using a decreasing size of aggregate helps to fill voids left by the larger aggregates in the lower layers, which enhances the overall compaction and stability of the seal. This layered approach improves the performance of the chip seal by ensuring that the top layer of smaller aggregate can effectively embed into the binder and also allows for better surface texture and drainage. Selecting larger aggregates for successive layers, as suggested by other options, could compromise the bonding and stability of the structure, leading to issues like segregation, inadequate sealing, and ultimately a shorter lifespan for the chip seal surface.

In a multiple chip seal application, the nominal aggregate size of each succeeding course being half the size of the previous course is a well-established practice aimed at achieving a proper interlock and effective compaction.

Using a decreasing size of aggregate helps to fill voids left by the larger aggregates in the lower layers, which enhances the overall compaction and stability of the seal. This layered approach improves the performance of the chip seal by ensuring that the top layer of smaller aggregate can effectively embed into the binder and also allows for better surface texture and drainage.

Selecting larger aggregates for successive layers, as suggested by other options, could compromise the bonding and stability of the structure, leading to issues like segregation, inadequate sealing, and ultimately a shorter lifespan for the chip seal surface.